The present invention relates to semiconductor design technology, and more particularly, to technology for controlling a set programming current and a reset programming current to program a phase change memory cell.
Although a dynamic random access memory (DRAM) device used as a main memory device of a computer can achieve random access and be highly integrated at low costs, it is volatile. A static random access memory (SRAM) device used as a cache memory device can achieve random access and operate faster than the DRAM device, but it is also volatile and has a disadvantage in an aspect of costs since its cell size is greater than that of the DRAM device. A NAND flash memory device, which is a non-volatile memory device, can be highly integrated at low costs and has an advantage in an aspect of power consumption, whereas it cannot achieve random access and has a low operating speed.
To overcome the disadvantages of the conventional memory devices, various memory devices are under development. Among them, a phase change random access memory (PCRAM) device has a non-volatile characteristic and can achieve random access and be highly integrated at low costs. The PCRAM device stores information using a phase change material. That is, the PCRAM device is a non-volatile memory device using a phase change of the phase change material according to a temperature requirement, i.e., the variation of a resistance value according to the phase change.
The phase change material includes a material that can be converted to an amorphous state or a crystalline state according to a temperature requirement. A representative phase change material is a chalcogenide alloy. The chalcogenide alloy includes Ge2Sb2Te5 (GST) using germanium (Ge), antimony (Sb) and tellurium (Te). Therefore, the phase change material is generally written up as GST.
The PCRAM device generates a convertibly phase change between a crystalline state and an amorphous state of the GST using joule heating generated by the supply of current or voltage in a certain condition for the GST. The crystalline state is referred to as a set state and the GST in the set state has an electrical characteristic like a metal having a low resistance value. The amorphous state is referred to as a reset state and the GST in the reset state has a higher resistance value than in the set state. That is, the phase change memory device stores information using the variation of resistance values between in the crystalline state and in the amorphous state and the stored information is detected by sensing a current flowing through the GST or the voltage variation according to the current variation. In general, it is defined that the set state has a logic level ‘0’ and the reset state has a logic level ‘1’, and the GST maintains its state although the power is not supplied thereto.
The amorphous state and the crystalline state are convertible to each other according to a programming current. A set current is defined as a programming current for making a GST of a memory cell a set state and a reset current is defined as a programming current for making the GST of the memory cell a reset state. For the reference, the set current may be referred to as a set programming current and the reset current may be referred to as a reset programming current.
The GST is heated to a temperature higher than a melting point thereof for a certain time by the supply of the reset current and then is rapidly cooled down to be converted to the amorphous state. Furthermore, the GST is heated at a temperature that is higher than a crystallizing point and lower than the melting point for a given time and then is gradually cooled down to be converted to the crystalline state. Meanwhile, it is possible to construct a multi-level memory cell since the resistance value can be graded according to an amorphous volume or a crystalline volume of the GST. In general, the reset current provides a big current for a short time compared to the set current, whereas the set current provides a small current for a long time compared to the reset current. Namely, the state of the GST is changed by the joule heating of a certain condition generated by the supply of the programming current.
FIG. 1 provides a schematic diagram of a phase change memory cell.
Referring to FIG. 1, the phase change memory cell includes a phase change element GST connected between a bit line BL and a first node N0 and a cell transistor MN1 connected between the first node N0 and a ground voltage terminal VSS and controlled by a word line WL.
An operation of the phase change memory cell illustrated in FIG. 1 will be described hereafter.
An operation of programming data in the phase change element GST is performed as described below.
If the cell transistor MN1 is turned on as the word line WL is activated to a logic high level, a current path is generated between the ground voltage terminal VSS and the phase change element GST connected to the bit line BL. Therefore, by supplying the phase change element GST with a programming current corresponding to the data through the bit line BL, a state of the phase change element GST is converted to a crystalline state or an amorphous state. If the data has a logic level ‘1’, a reset current is provided to the phase change element GST and thus the state of the phase change element GST is converted to a reset state. On the other hand, if the data has a logic level ‘0’, a set current is supplied to the phase change element GST and thus the state of the phase change element GST is converted to a set state. The reset state that is the amorphous state has a greater resistance value than the set state that is the crystalline state.
Moreover, an operation of detecting data programmed in the phase change element GST is performed as follows.
If the cell transistor MN1 is turned on as the word line WL is activated to a logic high level, a current path is generated between the ground voltage terminal VSS and the phase change element GST connected to the bit line BL. Thus, when supplying the phase change element GST with a certain voltage or current through the bit line BL, an amount of current flowing through the phase change element GST changes or an amount of a voltage drop across the phase change element GST changes according to the resistance value of the phase change element GST and, therefore, it is possible to detect the data stored in the phase change element GST using the amount of current or voltage drop. That is, the state of the phase change element GST is detected.
FIG. 2 describes a schematic diagram of another phase change memory cell.
Referring to FIG. 2, the phase change memory cell includes a cell diode D1 having a cathode connected to a word line WL and an anode connected to a first node N0 and a phase change element GST connected between a bit line BL and the first node N0.
An operation of the phase change memory cell illustrated in FIG. 2 will be described hereafter.
An operation of programming data in the phase change element GST is performed as described below.
If the word line WL is activated to a logic low level, i.e., a ground voltage level, and a predetermined voltage is supplied through the bit line BL, the cell diode D1 becomes in a forward bias state and thus the cell diode D1 is turned on from when a voltage difference between the anode and the cathode of the cell diode D1 becomes greater than a threshold voltage. At this time, a current path is generated between the word line WL and the phase change element GST connected to the bit line BL. Therefore, by supplying the phase change element GST with a programming current corresponding to the data through the bit line BL, a state of the phase change element GST is converted to a crystalline state or an amorphous state. If the data has a logic level ‘1’, a reset current is provided to the phase change element GST and thus the state of the phase change element GST is converted to a reset state. On the other hand, if the data has a logic level ‘0’, a set current is supplied to the phase change element GST and thus the state of the phase change element GST is converted to a set state. The reset state that is the amorphous state has a greater resistance value than the set state that is the crystalline state.
Furthermore, an operation of detecting data programmed in the phase change element GST is performed as follows.
If the word line WL is activated to the logic low level, i.e., the ground voltage level, and a certain voltage is supplied through the bit line BL, the cell diode D1 becomes in a forward bias state and thus the cell diode D1 is turned on from when a voltage difference between the anode and the cathode of the cell diode D1 becomes greater than a threshold voltage. At this time, a current path is generated between the word line WL and the phase change element GST connected to the bit line BL. Thus, when supplying the phase change element GST with a certain voltage or current through the bit line BL, an amount of current flowing through the phase change element GST changes or an amount of the voltage drop across the phase change element GST changes according to the resistance value of the phase change element GST and, therefore, it is possible to detect the data stored in the phase change element GST using the amount of current or voltage drop. That is, the state of the phase change element GST is detected.
As described in FIG. 2, the structure of the phase change memory cell using the cell diode D1 instead of the cell transistor is advantageous on high integration since it has an excellent characteristic of providing a programming current and occupies a small area. Therefore, the phase change memory cell is recently constructed with rather the cell diode than the cell transistor.
FIG. 3 illustrates a schematic circuit diagram of a conventional phase change memory device.
Referring to FIG. 3, the conventional phase change memory device includes a programming current adjusting block 310 and a programming current driving block 320.
The programming current adjusting block 310 adjusts a voltage level of a control node N4 in response to an enable signal WDEN and first and second write control signals SETEN and RESETEN. In particular, the programming current adjusting block 310 adjusts the voltage level of the control node N4 in response to a code combination of write control codes STEP<0:5> that is periodically updated during an activation period of the first write control signal SETEN, whereas it adjusts the control node N4 to have a predetermined voltage level during an activation period of the second write control signal RESETEN.
The programming current driving block 320 provides a phase change memory cell with a programming current I_PRO corresponding to the voltage level of the control node N4 through a transmission line SIO.
Herein, the first write control signal SETEN and the second write control signal RESETEN are selectively enabled in response to input data that is to be programmed.
Furthermore, the conventional phase change memory device may include precharge blocks 330A and 330B for precharging the control node N4 and an output node N0 of the programming current I_PRO, respectively, in response to a precharge signal /PCG. Herein, the precharge blocks 330A and 330B include a PMOS transistor MP0 connected between a supply voltage terminal VPPYWD and the control node N4 and controlled by the precharge signal /PCG, an inverter INV for inverting the precharge signal /PCG and an NMOS transistor MN0 connected between the output node N0 of the programming current I_PRO and a ground voltage terminal VSS and controlled by an output signal of the inverter INV. Since the precharge signal /PCG is a signal pulsing for a given period after the activation periods of the first write control signal SETEN and the second write control signal RESETEN, it is enabled at a point where the supply of the programming current I_PRO is terminated to thereby raise a voltage level of the control node N4 to a supply voltage VPPYWD, so that a PMOS transistor MP8 is turned off and thus the current driving to the output node N0 is stopped. As a result, the output node N0 is precharged with a ground voltage VSS.
The programming current adjusting block 310 includes an NMOS transistor MN7 connected between the control node N4 and a first node N1 and controlled by the first write control signal SETEN, a variable resistance sector 311 connected between the first node N1 and a second node N2 and controlled by the write control codes STEP<0:5>, a PMOS transistor MP9 connected between the control node N4 and a third node N3 and controlled by the ground voltage VSS, an NMOS transistor MN8 connected between the third node N3 and the second node N2 and controlled by the second write control signal RESETEN, and an NMOS transistor MN9 connected between the second node N2 and the ground voltage terminal VSS and controlled by the enable signal WDEN. Herein, the variable resistance sector 311 includes a plurality of load transistor groups MP1•MN1, MP2•MN2, MP3•MN3, MP4•MN4, MP5•MN5, and MP6•MN6 that are connected in parallel with each other and controlled by the ground voltage VSS and the write control codes STEP<0:5>. The plurality of load transistor groups include PMOS transistors controlled by the ground voltage VSS and NMOS transistors each of which is connected to a corresponding PMOS transistor among the PMOS transistors and controlled by a corresponding one among the write control codes STEP<0:5>.
The programming current adjusting block 310 adjusts the voltage level of the control node N4 in response to the enable signal WDEN and the first and second write control signals SETEN and RESETEN. That is, the voltage level of the control node N4 is adjusted by determining the number of NMOS transistors that are turned on among the NMOS transistors MN1 to MN6 according to the code combination of the write control codes STEP<0:5>, wherein the code combination is periodically updated during the activation period of the first write control signal SETEN. Furthermore, the control node N4 is adjusted to a preset voltage level since the NMOS transistor MN8 is turned on during the activation period of the second write control signal RESETEN.
The programming current driving block 320 serves as a current mirror and thus includes a plurality of transistors, e.g., MP7 and MP8, to drive a current corresponding to the voltage level of the control node N4. That is, the programming current driving block 320 includes the PMOS transistor MP7 that is connected between the supply voltage terminal VPPYWD and the control node N4 and has a gate node connected to the control node N4, and the PMOS transistor MP8 that is connected between the supply voltage terminal VPPYWD and the output node N0 and has a gate node connected to the control node N4. The amount of the programming current I_PRO outputted from the programming current driving block 320 is determined by the voltage level of the control node N4 and the channel size of the transistors MP7 and MP8.
Meanwhile, as described above, the phase change memory device, including one programming current adjusting block for simultaneously controlling the set state and the reset state and the programming current driving block for providing the phase change memory cell with the programming current, has a lot of limitations to independently control the set state and the reset state and needs one programming current adjusting block to control one programming current driving block. Therefore, the conventional phase change memory device requires programming current adjusting blocks as many as programming current driving blocks, so that a whole circuit area of the phase change memory device increases.